Recently in the field of radio frequency (RF) communications, there has been an increased demand for digitally encrypted voice and high speed data communications. Since the RF spectrum is inherently limited, one must devise a new system concept and organizational features to accommodate the increased demand. A time division multiple access (TDMA) system is one such system which offers more efficient spectrum utilization and increased capacity.
In its simplest form, a TDMA system is comprised of a transmitting base station, which is capable of time multiplexing messages from at least two users on a single RF channel, and one or more remote receiving stations capable of receiving at least one of the time multiplexed messages. Typically, the receiving station would be a mobile or portable radiotelephone capable of transmitting a TDMA message to the base station on a second RF channel.
In a TDMA system, like most digital communications systems, it is necessary to establish a reference clock in the receiving station that is continuously synchronized with the transmit clock in order to accurately recover the digital data transmitted between the two points. Continuous bit synchronization, as used herein, means that the frequency and phase of the received clock signal must accurately track that of the transmit clock.
Bit synchronization over a mobile communications channel can be difficult to maintain, primarily due to multipath fading. In addition to tracking the drift between the mobile and base station clocks, the clock recovery mechanism must be sufficiently tolerant of noise such that it does not readily lose synchronization during the periods of degraded signal-to-noise ratio caused by fading. Hence, an ideal TDMA mobile clock recovery circuit would have fast initial acquisition of symbol synchronization and continuously maintain synchronization with the base site clock, even during periods of severe signal fading.
One method which has been developed to provide a continuously synchronized clock signal for the mobile radiotelephone utilizes a phase-locked loop (PLL) to recover a clock in response to an appropriate bit rate timing signal derived from the received waveform. This circuit, however, would have difficulty maintaining synchronization during periods of severe fading. A second technique for clock recovery utilizes a programmable divider coupled to a reference clock signal. The recovered clock signal is compared to the received data signal, and the divide ratio is momentarily altered to shift the phase of the recovered clock. Again, this phase comparison technique would generally lose synchronization during a period of heavy fading.
Further developments have been made to address the problem of losing synchronization during a severe fade. One such method utilizes received signal strength information (RSSI) to determine when the received signal-to-noise ratio is poor due to a deep fade or signal dropout. When the RSSI falls below a predetermined threshold, the clock recovery phase shifting circuitry is disabled, thereby preventing random phase adjustment of the recovered clock signal.
Although this technique offers improved performance in fading, it has several problems. First, it requires an additional interface to the clock recovery circuitry for the RSSI. Second, additional circuitry is required to process the RSSI. Third, the RSSI threshold needs to be calibrated for each radio due to make tolerances in the RSSI circuitry. Finally, since this technique uses received signal strength as a channel quality indicator, it cannot detect poor channel quality caused by strong co-channel or adjacent channel interference. During this time the recovered clock may jitter randomly and lose synchronization.
Therefore, a need exists for a clock recovery circuit which will maintain continuous synchronization with the base station transmitting clock without the problems associated with the aforementioned techniques.